Design For Testability M.Tech Question Paper : vardhaman.org

College : Vardhaman College Of Engineering
Degree : M.Tech
Semester : II
Department : Electronics and Communications Engineering
Subject : Design For Testability
Document type : Question Paper
Website : vardhaman.org

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Vardhaman Design For Test ability Question Paper

(Digital Electronics and Communications Systems)
Date: 18
Time: 3 hours
Max Marks: 60
Answer any Five Questions.
All Questions carry equal marks.

Related : Vardhaman College Of Engineering Low Power Cmos VLSI Design M.Tech Question Paper : www.pdfquestion.in/6455.html

July –  2014

All parts of the question must be answered in one place only.

1. a) Explain the construction of state tables and flow tables for synchronous and asynchronous sequential circuit taking few examples. 6M
b) Draw the Bipartite graph model for the circuit shown in Fig.1. Also construct ELEMENT TABLE, SIGNAL TABLE,FANIN TABLE and FANOUT TABLE for the same circuit.

2. a) Explain Transport Delays and Inertial Delays in detail. 6M
b) Explain how to construct Zoom Tables and given a few advantage of zoom tables.
Outline typical Gate evaluation routine for 3-valued logic based on scanning the input values and based on input counting method. 6M

3. a) For the circuit shown in Fig.2 6M
i. Find the set of all tests that detect the fault a s – a – 0
ii. Find the set of all tests that detect the fault b s – a – 0
iii. Find the set of all tests that detect the multiple fault { a s-a-0, b s-a-0}

b) Explain briefly the following terms :
i. Sensitization
ii. Detectability
iii. Redundancy 6M

4. a) Explain concept of ATG in combinational circuit using Fanout-Free circuit. 6M
b) Explain Vector simulation, vector compaction and compression in detail. 6M

5. a) Explain generic boundary scan and fully integrated scan with neat diagrams. 6M
b) With neat diagrams, explain Board-Level and System level DFT Approaches. 6M

6. a) Explain Ones- Count compression technique in detail. 6M
b) Explain how LFSR is used in signature analysis compression technique. 6M

7. a) How a built-in-self test is classified? Give some examples. 6M
b) Explain BIST designs with BILBO register. And also explain Bus-oriented and Pipelineoriented BILBO architecture. 6M

8. a) With neat diagrams explain different types of memory and Key Issues in Memory Integration. 6M
b) Explain the following:
i. JTAG testing features
ii. Memory chip test algorithms 6M

February – 2014

M. Tech II Semester Supplementary Examinations,
DESIGN FOR TESTABILITY
(Digital Electronics and Communication Systems)
Date : 15 February, 2014
Time : 3 Hours
Max. Marks : 60
Answer any FIVE Questions.
All Questions carry equal marks

All parts of the question must be answered in one place only
1. a) Construct a binary decision diagram for the following:
i. Exclusive OR function of two variable
ii. Exclusive NOR function of two variable 6M
b) Write two RTL model for a positive edge triggered D Flip Flop. First assume an RTL that does not allow accessing past values of signals. Remove the restriction for the second model. 6M

2. a) Explain the following with examples
i. Delay modeling for gates
ii. Delay modeling for functional elements 6M

b) Construct a Zoom table for evaluating AND, OR, NAND and NOR gates with two inputs with Binary values. 6M
3. For the circuit of Fig. 1: Fig
i. Find the set of all tests that detects the fault ‘c’ at stuck at 1
ii. Find the set of all tests that detects the fault ‘a’ stuck at 0
iii. Find the set of all tests that detects the multiple fault {‘c’ at stuck at 1, ‘a’ stuck at 0} 12M

4. a) Construct a truth table for an XOR function of two input using the five logic values 0, 1, x, D, and D’. 6M
b) Show that the expected fault coverage of a random test sequence of length N is greater than:
i. its testing quality tN
ii. its detection quality dN 6M

5. a) Using Huffman model for sequential circuit, explain full integrated scan. 6M
b) Explain isolated serial scan.

6. a) Explain the following compression techniques:
i. Ones count compression
ii. Transition count compression 6M
b) For an autonomous LFSR show that if it’s initial state is not all 0 state then it will never enter the all 0 state. 6M

7. a) Show that complementing one column of a matrix representing a pseudoexhaustive test set creates a test set that is also pseudoexhaustive. 6M
b) Prove that for a case where p=w+1, applying all possible binary patterns of p bits with either odd or even parity will either produce a test set where for every subset of w lines all possible binary patterns will occur. 6M
8. a) Explain random test data (RTD) BIST architecture. 6M
b) List the memory test requirements for Memory BIST.