EC010504 Electric Drives & Control B.Tech Model Question Paper : mgu.ac.in

Name of the University : Mahatma Gandhi University
Department : Mechanical Engineering
Degree : B.Tech
Subject Code/Name : EC 010 504/Electric Drives And Control
Sem : V
Website : mgu.ac.in
Document Type : Model Question Paper

Download Model/Sample Question Paper : https://www.pdfquestion.in/uploads/mgu.ac.in/5353-EC%20504(1).doc

MGU Electric Drives & Control Model Question Paper

B.TECH Degree Examination November 2012 :
Fifth Semester :
Branch: Electronics and Communication Engineering
EC 010 504 Electric Drives And Control :
Time:Three Hours
Maximum : 100 Marks

Related : Mahatma Gandhi University Thermodynamics B.Tech Model Question Paper : www.pdfquestion.in/5352.html

Part A :
Answer all questions :
1. Derive the emf equation of a DC machine.
2. Explain the torque-slip characteristics of a three phase induction motor.
3. Compare power MOSFET and BJT.
4. What is the basic principle of PWM?
5. Discuss about chopper fed drives. (5 × 3 = 15 marks)
Part B :
Answer all questions :
6. Explain the need for starter with a DC motor.
7. Draw and explain the equivalent circuit of a two winding transformer.
8. Discuss different specifications of an SCR.
9. Explain the role of a free wheeling diode in a single phase half controlled circuit with R-L load.
10. Explain two and four quadrant drives. . (5 × 5 = 25marks)

Part C :
11. (a) Explain the different types of DC Generators and its applications. (5 marks)
(b) A dc shunt generator gave the following open-circuit characteristic when drven at 750 rpm.
Field Current (A) : 0.5 1 1.5 2 2.5
Emf (V) : 50 84 105 120 131
(i) If the machine is run as a shunt generator at 750 rpm, to what voltage will it excite with shunt field resistance equal to 80 ? ?
(ii) What is the critical value of shunt field resistance?
(iii) What is the critical speed when the shunt field resistance is 80 ? ? (7 marks)
OR
12. (a) Draw the expression for torque developed in a DC motor. (4 marks)
(b) Explain Swinburne’s test for determining the efficiency of a DC machine. State its advantages and disadvantages. (8 marks)

13 .(a) In a 50 kVA transformer, the iron loss of 450 W and full-load copper loss of 850 W.
Find the efficiency at full-load and half full-load at 0.8 p.f. lagging. (7 marks)
(b) Explain the working of a Synchronous motor (5 marks)
OR
14.(a) Draw and explain the phasor diagram of a single phase transformer for resistive load. (5 marks)
(b)What are the different classifications of single phase induction motors? Explain each. (7 marks)
15.(a) Explain the two transistor analogy of an SCR. (6 marks)
(b) Explain the static characteristics of a MOSFET ( 6 marks)
OR
16.(a) With neat diagram explain the RC triggering circuit of an SCR.? (6 marks)
(b) What is an IGBT? Explain its characteristics. (6 marks)
17.(a) Explain the principle of phase control. (4 marks)
(b)Explain the operation of a single phase fully controlled bridge circuit with RLE load. (8 marks)
OR
18.(a) Explain the characteristics and features of current source inverters. Compare VSI and CSI.
(8 marks)
(b) Draw the block diagram of UPS and explain its principle of operation. (4 marks)
19. Explain in detail speed control of 3 phase induction motors and give the principle. (12 marks)
OR
20. With neat waveforms, explain the operation of a single phase fully controlled bridge rectifier dc drive. Derive the performance parameters. (12 marks)

Digital System Design

Time : 3 Hrs
Max Marks: 100

Part A

(Answer all questions. Each question carries 3 marks)
1. What are the different data types in Verilog HDL?
2. Draw the structure of 8:1 decoder.
3. Define metastability.
4. Explain ASM in brief.
5. What is a test bench? What is its relevance in Verilog?

Part B

(Answer all questions. Each question carries 5 marks)
6. Write the verilog code for a 2:4 decoder circuit.
7. Realise the functions f1(x,y,z) = ?m(1,2,4,5) and f2(x,y,z) = ?m(1,5,7) using MUX.
8. With a neat block diagram, explain Mealy and MOORE model.
9. Explain the relevance of implication table in state machine concepts.
10. Explain the different types of modelling in Verilog.

Part C

(Each question carries 12 marks)
11. Design and implement 16:1 Multiplexer using two 8:1 MUX in Verilog HDL.
OR
12. Design and implement a full adder using Verilog HDL.
a) gate level modelling
b) Structural modelling( using half adder)

13. Simplify the given Boolean function F(A,B,C,D) = m(0,1,2,8,10,11,14,15) using Quine Mc Clusky algorithm.
OR
14. a) With a neat block diagram, explain PLA. ( 4 marks)
b) Implement the functions, f1(x,y,z) = fm(1,2,3,7) and f2(x,y,z) = fm(0,1,2,6) using 3X4X2 PLA ( true/compliment method). (8 marks)

15. Design a clocked synchronous sequential circuit which detects the following sequence 0110/1001.
OR
16. Design and implement a serial binary adder as a Mealy network.