07A80305 Computer Organization & Architecture B.Tech Question Paper : scce.ac.in

Name of the College : SREE CHAITANYA COLLEGE OF ENGINEERING
University : JNTUH
Department : Mechanical Engineering
Subject Code/Name : 07A80305/COMPUTER ORGANIZATION AND ARCHITECTURE
Year/Sem : IV/II
Website : scce.ac.in
Document Type : Model Question Paper

Download Model/Sample Question Paper : https://www.pdfquestion.in/uploads/scce.ac.in/4919-07A80305-COMPUTERORGANIZATIONANDARCHITECTURE.pdf

SCCE Computer Organization Question Paper

Code No: 07A80305
R07 Set No. 2
IV B.Tech II Semester Examinations,April/May 2012

Related : Sree Chaitanya College Of Engineering 07A80206 Object Oriented Programming B.Tech Question Paper : www.pdfquestion.in/4927.html

Common to Mechanical Engineering, Automobile Engineering
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions :
All Questions carry equal marks :
1. (a) What is the function of a Multiprocessor system and list out the various characteristics of Multiprocessors?
(b) Explain how the Multiprocessors are classified based on their memory organization. [10+6]

2. (a) What is implied mode, immediate mode, register mode, register indirect mode, auto increment and auto decrement mode.
(b) What is Zero address instruction, one address instruction? [8+8]

3. (a) With a neat diagram, discuss in detail about the possible address assignment for a byte-addressable 32-bit computer.
(b) Draw the block diagram showing various connections of the main memory to the CPU. Also, explain about issues related to their bus structures. [7+9]

4. A computer uses a memory unit with 256K words of 32bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, register code part to specify one of 64 registers, and an address part.
(a) Draw the instruction word format and indicate the number of bits in each part.
(b) How many bits are there in data and address inputs of memory? [16]

5. (a) What is the function of a FIFO buffer?
(b) Draw the complete circuit diagram of 4 FIFO buer and explain it in detail. [1+15]

6. (a) What is the dierence between microprocessor and micro program? Is it possible to design a microprocessor without a micro program? Are all micro programmed computers also microprocessors?

(b) Explain the dierence between hardwired control and micro programmed control. Is it possible to have a hardwired control associated with a control memory? [8+8]

7. Represent decimal number 7777 in:
(a) BCD
(b) excess – 3 code
(c) 2421 code. [16]

8. (a) How do you determine the number of clock cycles that it takes to process 200 tasks in a six-segment pipeline.
(b) Mathematically, show that the theoretical maximum speedup that a pipeline can provide is `K’, where `K’ is the number of segments in the pipeline.[6+10]

Code No: 07A80305
R07 Set No. 4
1. Explain the significance of RISC system. Does RISC support. Complex instruction set computer concepts and operations. [16]
2. Explain with block diagram the typical functional blocks of a computer system,and explain the computer types with respect to the functional blocks. [16]

3. (a) Consider a single-transistor dynamic memory cell. Assume that C = 50 fentofarads and the leakage current through the transistor is about 9 pico amperes. The voltage across the capacitor when it is fully charged is equal to 4.5V. The cell must be refreshed before this voltage drops below 3V. Estimate the minimum refresh rate.

(b) Discuss in detail about various features of ROM, PROM and EPROM.[6+10]
4. (a) With a neat block diagram, explain about one possible way of seperating the execution unit into eight functional units operating in parallel.

(b) Bringout atleast two dierences between (i) SSID & SIMD (ii) MISD & MIMD.[8+8]
5. Using a 4bit counter with parallel load and 4 bit address, draw a block diagram that shows how to implement the following statements and explain:
x: R1<- R1 + R2 //Add R2 to R1
x y : R1<- R1 +1. // Increment R1 [16]

6. (a) With a neat block diagram explain the various processes involved in system bus structure for multi processors.
(b) What is the function of a cross bar switch network and how many switch points are there in a cross bar switch network that connects `P’ processors to `m’ memory modules? [10+6]

7. A computer has 16 registers an ALU, with 32 operations and a shifter with eight operations, all connected to a common bus system
Show the bits of the control word that specify the micro operation R4 < – R5 +R6. [16]

8. (a) Draw the truth table of a four-input priority encoder and explain it in detail.
(b) Design a parallel priority interrupt hardware for a system with eight interrupt sources. [6+10]