MIT2004 Computer Architecture M.Sc Question Bank : uou.ac.in
Name of the University : Uttarakhand Open University
Degree : M.Sc
Department : Information Technology
Subject Code/Name : MIT2004 Computer Architecture
Document Type : Model Question Papers
Website : uou.ac.in
Download Model/Sample Question Paper : https://www.pdfquestion.in/uploads/uou.ac.in/4636.-MIT-2004.pdf
Computer Architecture :
MSc- IT-10 (Master of Science in Information Technology
Time : 3 Hrs
Max Marks : 60
Related : Uttarakhand Open University MIT2003 Advance Java Programming M.Sc Model Question Paper : www.pdfquestion.in/4637.html
Section A
Long Answer Type Questions
1. Find the value of number 12389 in
(i) 10’s complement form(ii) 9’s complement form
(iii) 1’s complement form(iv) 2’s complement form.
2. Perform the arithmetic operations (+42)+(-13) and (-42)-(-13) in binary
3. What is the difference between isolated and memory mapping-
4. Define booth’s algorithm for multiplication.
Section B
Short Answer Type Questions
4X5=20 Marks
1. What is the difference between a vectored interrupt and non-vectored
2. What is a difference between a serial and parallel data transmission-
3. Definea. Page faultb. Logical address
4. Define locality of reference.
5. What is floating point notation- What is benefit of these-
6. What are vector processors-
7. What are the different types of computer instruction- Explain.
8. Explain the functioning of master-slave flip flop.
Section C
Objective Question
10×1=10 marks
1. Arithmetic and logical operations are performed by :
a. Hard disk b. Floppy disk
c. CPU chip d. Memory chip
2. The register which stores the address of the next instruction
a. Memory Address Register b. Memory Data
c. Instruction Register d. Program Counter
3. A complete microcomputer system consists of :
a. microprocessor b. memoryc. peripheral equipment d. all of above
4. ALU performs :
a. arithmetic operations b. logic operation
c. shift operation d. all of above
5. Pipelining strategy is called implement :
a. instruction execution b. instruction prefetch
c. instruction decoding d. instruction manipulation
6. A stack is :a. an 8-bit register in the microprocessor
b. a 16-bit register in the microprocessor
c. a set of memory locations in R/WM reserved for storing
d. a 16-bit memory address stored in the program counter
7. A stack pointer is :
a. a 16-bit register in the microprocessor that indicate the beginning
b. a register that decodes and executes 16-bit arithmetic expression.
c. The first memory location where a subroutine address is stored.
d. a register in which flag bits are stored
8. The branch logic that provides decision making capabilities
a. controlled transfer b. conditional transfer
c. unconditional transfer d. none of above
9. Interrupts which are initiated by an instruction are :
a. internal b. external
c. hardware d. software
10. A time sharing system imply :
a. more than one processor in the systemb. more than one program
c. more than one memory in the systemd. None of above
Second Semester Examination-2015 :
MCA-05/M.SC.(IT)-05/PGDCA-05
Computer Organization & Architecture :
Time : 3 Hours
Maximum Marks : 60
Note : This paper is of sixty (60) marks divided into three (03) sections A, B, and C. Attempt the questions contained in these sections according to the detailed instructions given therein.
Section – A : (Long Answer Type Questions)
Note : Section ‘A’ contains four (04) long-answer-type questions of fifteen (15) marks each. Learners are required to answer any two (02) questions only. (2×15=30)
1. Explain Wormhole routing for message-passing technique
2. (a) Write briefly about interrupt? How to handle multiple interrupts.
(b) Discuss the Instruction Execution Cycle without interrupt and with interrupt
3. What do you mean by Addressing Mode? Discuss different types of addressing modes including the advantages and disadvantages of each mode.
4. Discus the basic concepts of pipelining. What is a pipeline hazard? What are the types of hazards?
Section – B : (Short Answer Type Questions)
Note : Section ‘B’ contains eight (08) short-answer-type questions of five (05) marks each. Learners are required to answer any four (04) questions only. (4×5=20)
1. What is the difference between parallel processing and pipeline processing?
2. Discuss about the Hardwired implementation of the Control Unit.
3. What is Bus? Draw the single bus structure.
4. What are the methods for determining which I/O device has requested an interrupt?
5. State and explain in brief Flynn’s classification of Multiprocessor architecture.
6. Explain the concept of Virtual Memory.
7. What do you mean by locality of reference? What are its types?
8. Discuss memory disk caching with level 1 and level 2 cache.
Section – C : (Objective Type Questions)
Note : Section ‘C’ contains ten (10) objective-type questions of one (01) mark each. All the questions of this section are compulsory. (10×1=10)
1. In memory-mapped I/O
a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
2. In case of, Zero-address instruction method the operands are stored in ………… .
a) Registers
b) Accumulators
c) Push down stack
d) Cache
3. The method of access ing the I/O devices by repeatedly checking the status flags is
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None
4. The bus connecting CPU, Memory and I/O is known as
a) Bus
b) System Bus
c) Modem
d) None of the above
5. The DMA differs from the interrupt mode by
a) The involvement of the processor for the operation
b) The method accessing the I/O devices
c) The amount of data transfer possible
d) Both a and c