MVN ECL505 Digital Communication Techniques M.Tech Previous Year Question Paper

Name of the College : MVN University
Department : Electronic Communication And Engineering
Subject Code/Name : ECL 505-Digital Communication Techniques
Year : Dec.2012 – Jan.2013
Degree : M.Tech
Sem : I
Website : mvn.edu.in
Document Type : Previous Year Question Paper

Download Model Question Paper : https://www.pdfquestion.in/uploads/mvn.edu.in/3105-DCT(1).pdf

MVN Communication Techniques Previous Question Paper

Time Allowed: 03 hours.
Maximum Marks: 100

Related : MVN University CSL507 Advance C/C++ Programming M.Tech Question Paper : www.pdfquestion.in/3099.html

Instructions

Before answering the question paper the candidate should ensure that they have been supplied the correct question paper. Complaints in this regard, if any, shall not be entertained after the examination.

Note: Attempt any five questions and all questions carry equal marks.

January 2014

Section – A :
1 (a) What are the properties of a signal? Compare analog signal with digital signal. [10]
(b) Classify channels. Explain the model of any two communication channels. [10]
2 (a) Explain the block diagram of digital communication system. [10]
(b) Consider the vectors {(1, 1, 0), (1, 0, 1), (0, 1, 1), (1, 1, 1)} [10]
i) Why can these vectors not be linearly independent?
ii) Carry out the Gram-Schmidt process.
3 (a) State and explain with relevant waveforms Pulse code modulation. [10]
(b) Explain DPCM with neat diagrams for transmitter and receiver with mathematical models. [10]

Section – B :
4 (a) Derive the bit error probability due to coherent ASK,PSK and FSK systems. Compare the performance of these systems. [10]
(b) Discuss QPSK signaling. Compare the performance of QPSK receiver with that of PSK receiver. [10]
5 (a) Define linear block codes .Find the (7, 4) linear systematic block code word corresponding to 1101.Assume a suitable generator matrix. [10]
(b) Assume a (2, 1) convolutional coder with constraint length 6.
Draw the tree diagram, state diagram and trellis diagram for the assumed coder. [10]
6. Give a detailed note on Communication networks. [20]

June 2013

Advanced Digital Signal Processing
Subject Code: ECL-503
Time Allowed: 03 hours.
Maximum Marks: 100
Note
Before answering the question paper the candidate should ensure that they have been supplied the correct question paper.
Complaints in this regard, if any, shall not be entertained after the examination.
Attempt any five questions and all questions carry equal marks.

Section – A :
1(a) Differentiate between FIR and IIR digital filters.
(b) Obtain the direct form I and II for given transfer function H(Z) of IIR filter:

2(a) Why do we require multirate DSP. Write three applications of M DSP.
(b) Transfer function H(S) of an analog filter is given at T=2 seconds: Convert it into digital filter using bilinear transformation method.

3(a) Discuss the forward and backward linear prediction.
(b) What is AR, MA and ARMA lattice? Explain any one. Section – B

4(a) Define FFT. Calculate 8 point DFT using FFT.
(b) Describe chirp-z transform algorithm. What is its importance?

5(a) What do you understand by FIR hardware? Explain its different form.
(b) Justify the need of multipliers and dividers in signal processing hardware.

6(a) Discuss the model of Speech production.
(b) Describe the linear prediction of speech.

January 2012

Digital Electronics
Subject Code: ECL-203
Time Allowed: 03 hours.
Maximum Marks: 100
Note :
** Before answering the question paper the candidate should ensure that they have been supplied the correct question paper.
** Complaints in this regard, if any, shall not be entertained after the examination.
** Question No. 1 is Compulsory and attempt two questions from each section. All questions carry equal marks.

Section A :
1 i) Convert the decimal number 124 in
(a) BCD (b) Gray Code (c) Excess-3 (3)
ii) Perform (14)10 – (29)10 using 2’s complement. (3)
iii) Implement the OR gate Expression using NAND Gate? (3)
iv) Implement the AND gate expression using NOR? (3)
v) What is the difference between combinational & sequential logic? (4)
vi) Write the difference between SRAM and DRAM? (4)

2(a) Construct the Hamming code for 1011 for even parity. (6)
(b) Realize & implement the parity checker circuit for odd parity. (8)
(c) Simplify the following (6)

3(a) Implement the EX-OR & Ex-NOR Gate Expression using NAND & NOR Gate? (10)
(b) Reduce the following function using k-map technique (10) F(A,B,C,D)= M(0,3,4,7,8,10,12,14)+d(2,6)

4(a) Implement the full adder circuit using 8:1 MUX. (10)
(b) Design a Binary to gray code converter? (10)

Section – B :
5(a) Find out the following for a given state transition diagram:- (15)
State table
State reduction
(b) What is the significance of excitation table? (5)

6(a) Implement the full adder circuit using PAL. (14)
(b) What is PLA? Explain with block diagram. (6)

7(a) write short note on any two of the following: (14)
• Hazards
• designing procedure ASL circuits
• FPGA

(b) What is the difference between primitive & Non-primitive flow table? (6)