14CS2005 Computer Architecture B.Tech Question Bank : karunya.edu

Name of the College : Karunya Institute of & Sciences
University : Kaunya University
Degree : B.Tech
Department : Information
Subject Name : Computer Architecture
Document Type : Question Bank
Website : karunya.edu

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Computer Architecture Question Paper

Part – A

1. What is stored program concept?
2. Differentiate memory write and I/O write.
3. What are the various methods of accessing data from memory?

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4. Define memory cycle time.
5. State the different phases of instruction cycle.
6. What is indirect indexed addressing?
7. What are the fields or flags contained in a PSW?
8. Name few approaches to deal with conditional branching while pipelining.
9. What is a micro operation?
10. What is the use of control memory?
11. List out the basic functions that a computer can perform.
12. List out the performance parameters of memory.

Part – B

13. ________________memory is read and written electrically as with PROM.
14. List out the requirements for an I/O Module.
15. Give the rule for forming the negation of integer in sign-magnitude representation.
16. The collection of different instructions that the CPU can execute is referred to as the CPU’s ________________.
17. ________________ contains the instruction most recently fetched.
18. What is loop buffer?
19. ________________ Control unit contains complex logic circuitry for sequencing through the many micro operations of the instruction cycle.
20. Classify micro instructions.
21. ____________ and ______________ are stored in a single read write memory.
22. External memory capacity is typically expressed in terms of ______________.
23. Adjacent tracks are separated by____________.
24. Convenience and efficiency are two objectives of ____________.
25. An instruction format defines the layout of the bits of an ______________.
26. Define Write data.
27. Expand HLL.
28. Expand RISC.
29. The organization of a multiprocessor system can be classified as ____________.
30. Expand PVR.
31. Fetched instruction is loaded into a register in the processor known as ———————–.
32. In a ——————— memory, information decays naturally or is lost when electrical power is switched off.
33. List out the drawbacks of programmed and Interrupt-driven I/O.
34. The ————————— converts data from electrical to other forms of energy during output and from other forms to electrical during input.
35. State the rule for finding negation of an integer in Two’s Complement notation.
36. List out basic logical operations.
37. List out two categories of CPU registers.
38. What is programmed Exception ?
39. ————————– holds the address of the next instruction to be fetched.
40. List out the two basic tasks that control unit perform.
41. A processor whose elements have been miniaturized into one or a few integrated circuits is called _________.
42. The collection of paths connecting the various modules is called the _________.
43. A more attractive form of read-only memory is _________.
44. Data are transferred to and from the disk in _________.
45. _________ instructions operate on the bits of a word as bits rather than as numbers.
46. The _________ has a 36 bit word length and a 36 bit instruction length.
47. _________ contains the address of a location in memory.
48. _________ contains a variety of status and condition bits.
49. _________ are the functional or atomic operations of a processor.
50. The set of microinstructions is stored in the _________.
51. ________ is a popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus.
52. ________ is intended to give memory speed approaching that of the fastest memories available, and at the same time provides a large memory size at the price of less expensive types of semiconductor memories.
53. In a ________, there is one read-write head per track.
54. An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an ________.
55. When ________ occurs, the ALU must signal this fact so that no attempt is made to use the result.
56. A ________ is one in which the most significant digit of the significant is zero.
57. ________ contains the address of an instruction to be fetched.
58. Internal memory consisting of a set of storage locations called ________.
59. ________ module interfaces to devices that communicates 1 bit at a time.
60. The ________ contains the address of the next micro instruction to be read.
61. What is a Peripheral?
62. What is an Interrupt Request Signal?
63. Why is associative access fast?
64. State the applications of SRAM and DRAM.
65. State the Overflow Rule.
66. What is an Assembler?
67. State the need for Internal Processor Bus.
68. List the reasons, which complicate the design and use of Pipelines.
69. What is the purpose of MBR?
70. What are Hard Microprograms?
71. ________ register contains the word to be stored in memory, or is used to receive a word from memory.
72. ________ contains the address of next instruction to be fetched from memory.
73. _____________ is the volatile memory.
74. In ________ mode the IO module and main memory exchange data without processor involvement.
75. In ________ addressing mode the operand is present as a part of instruction.
76. Write the formula for register addressing mode.
77. ________ contains the instruction most recently fetched.
78. In ________ register of Pentium processor contains condition codes and mode bits.
79. What is the use of MAR?
80. What are the two main task performed by micro programmed control unit?
81. ________ holds the address of the next instruction to fetch.
82. ________ provides storage internal to the CPU.
83. How are bits stored in dynamic RAM?
84. 8086 based systems use one ________ interrupt controller.
85. Which bit is designated as the sign bit in the signed magnitude representation of an integer?
86. What is immediate addressing?
87. Why are general purpose registers present in CPU?
88. What is PSW?
89. Mention the two types of control unit.

Part – C

90. A sequence of microinstructions is known as micro-program or ________.
91. What is meant by function?
92. Define Interrupt.
93. Define Transfer Rate.
94. List out the drawbacks of programmed interrupt I/O.
95. What is Sign Magnitude Representation?
96. Define instruction set.
97. What general roles are performed by CPU registers?
98. What is a Program Status Word?
99. Define Micro Operations.
100. What is the function of program counter?
101. List out the main structural components of a Computer.
102. What is the expansion for HPC.
103. The two traditional forms of RAM used in computers are _______.
104. What is a Buffer?
105. DOUBLE represents how many numbers of bits in IEEE745 format?
106. Write the basic algorithm for Indirect addressing mode.
107. What is the function of a Stack pointer?
108. Which instruction is used to determine the opcode and the operand specifiers?
109. Give the full form for MAR and MBR.
110. List out the restart instructions available in 8085 microprocessor.
111. State the significance of a Cache memory.
112. List any two exceptional conditions that cause trap interrupts.
113. Classify the storage devices based on speed.
114. Differentiate RAM and ROM.
115. Define assembly level language.
116. Differentiate an operand and an operator with an example.
117. State the definition and role of a register.
118. Name the major phases of a RISC pipeline.
119. Draw the generic format of a control unit.
120. Categorize microinstructions based on their size.
121. What is hardwired program?
122. Number of blocks in main memory is ———————— if number of bits used to address a word is ‘n’ and the number of words in a fixed block is ‘K’?
123. State drawbacks of Interrupt-driven I/O.
124. What is SDRAM? How is it different from DRAM?
125. Compute (1.0000000010 x 25) – (1.0000000000 x 2-2) and normalize the results.
126. State the difference between arithmetic shift and logical shift.
127. State the usage of branch history table in pipelining.
128. A pipelined processor with 5 stages executes a program with 10000 instructions which are issued at a rate of one/clock cycle. What is the speedup factor of this processor compared to non-pipelined processor?
129. Give an example of a horizontal microinstruction.
130. Show the micro-operations for ‘Indirect Cycle’