RR410506 Fault Tolerant Systems B.E Question Paper : djriet.edu.in

Name of the College : Dasari Jhansi Rani Institute Of Engineering And Technology
University : JNTUK
Department : Computer Science And Engineering
Subject Code/Name : RR410506 – Fault Tolerant Systems
Year : 2008
Degree : B.E
Year/Sem : IV/I
Website : djriet.edu.in
Document Type : Model Question Paper

Fault Tolerant Systems : https://www.pdfquestion.in/uploads/dmice.ac.in/2829-RR410506-FAULT-TOLERANT-SYSTEMS.pdf

DJRIET Fault Tolerant Systems Question Paper

Set – I

( Common to Computer Science & Engineering and Electronics & Computer Engineering)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions :

Related : Dasari Jhansi Rani Institute Of Engineering And Technology RR410501 Software Engineering B.E Question Paper : www.pdfquestion.in/2827.html

All Questions carry equal marks :
1. (a) A computer system contains 10,000 components each with failure rate 0.5% per 1000 hours. What is the period of 0.99 reliability of this system. [6]
(b) What is meant by active repair time and passive repair time referred in maintainability of a system. Derive the expression for the MTTR. [3+3+4]
2. (a) A circuit realizes the function.
Z=X1 X4+X2 X3+X1X4
Using Boolean Difference method find the test vectors for SA0, SA1 faults on all input lines of the circuit.
(b) What are the different properties of Boolean differences? Explain. [5+5+6]

3. (a) Design a redundant circuit for f = ab + a’b’
(b) Explain the Dynamic redundancy Technique of a fault Tolerant system.[8+8]
4. (a) What is the mechanism adopted in COPRA a fault Tolerant system. Explain in detail.
(b) What is meant by Time redundancy? Explain. [4+4+4+4]
5. Design a totally self-checking checker for maximal-length Berger codes also give the procedure to generate test vectors of 8 bit long. [8+8]
6. Explain the steps to derive G-functions which generates the Ci() check bits in modified Berger code specially for detecting uni-directional output errors in PLAs. Take an example to explain the above steps. [16]
7. (a) Explain three level OR-AND-OR design technique.
(b) Write a short note on adding control logic in to a combinational logic to have only 5 test pattern. [8+8]
8. (a) Draw the logic diagram of Hazard-free polarity hold latch, and explain with the help of flow table & excitation table. [2+2+2]
(b) Draw the logic diagram of shift register latch and explain its principle. Using above latch. [3+7]

Set – II

1. (a) Distinguish between failures, and faults ? Explain. [2+2]
(b) Explain the different modeling schemes of faults that generally come across in digital circuits. [3 × 2]
(c) Explain the following terms with respect to digital circuits with suitable examples.
i. Fault diagnosis.
ii. Fault detection test set.
iii. Test vector generation. [3 × 2]
2. (a) A circuit realizes the function.
Z=X1 X4+X2 X3+X1X4
Using Boolean Difference method find the test vectors for SA0, SA1 faults on all input lines of the circuit.
(b) What are the different properties of Boolean differences? Explain. [5+5+6]
3. (a) Construct a seven-bit error correcting code to represent the decimal digit by augmenting the Excess-3 code and by using add-1 parity check.
(b) Design a redundant circuit for f = a b [9+7]
4. (a) What is the goal of “pluibus” system used in ARPA network. Explain its working.
(b) What is ment by fail soft operation? What should a system have to achieve the capability of fail soft operation. [4+4+4+4]
5. (a) What is the need for self checking circuits
(b) Design a totally self checking checker by using reddy’s partition method for 2out of 5 code. [6+10]
6. (a) Explain the general appraoch to the design of totally self-checking PLAs.
(b) Explain why self-checking machines are essential in digital system. [10+6]
7. (a) What are the draw backs of Reed-Muller expansion Technique.
(b) What is an unate function?
(c) Give the design procedure for a completely fault locatable networks for unate function. [6+4+6]
8. (a) What is meant by built in test of VLSI? Explain.
(b) Discuss the crosscheck approach to incorporate test circuitry into the basic cells used in implement VLSI design. [8+8]

Set – III

Answer any FIVE Questions
All Questions carry equal marks
1. (a) Define the term Reliability of a system. Derive a relation for the R(t) in terms of constant failure rate ?. [3+5]
(b) What is meant by Mean time between failures? How is it useful in system usage. Derive the expression of MTBF. [2+3+3]
2. For the circuit shown as in figure 2 , derive
(a) minimal complete fixed scheduled fault detection experiment.
(b) minimal complete fixed scheduled fault location experiment. [8+8]
3. (a) Construct a seven-bit error correcting code to represent the decimal digit by augmenting the Excess-3 code and by using add-1 parity check.
(b) Design a redundant circuit for f = a b [9+7]

4. (a) Explain in detail the practicle fault Tolerant space shuttle computer complex system.
(b) What are the different ways to have software redundancy. [8+8]
5. (a) What is the need for self checking circuits
(b) Design a totally self checking checker by using reddy’s partition method for 2out of 5 code. [6+10]

6. (a) Explain the advantages of PLA and how it is used as totally self-checking circuit.
(b) For the given 4 input, 4 output function design a totally self checking checkercircuit using PLAs. [6+10] f1 (A,B,C,D) = P (0,2,3,7,8,10,12,13,15)