CS7103 Multicore Architecture M.E Question Bank : valliammai.co.in

Name of the College : Valliammai Engineering College
University : Anna University
Department : Computer Science and Engineering
Subject Code/Name : CS7103 Multicore Architecture
Degree : M.E
Year : I
Semester : I
Document Type : Question Bank
Website : valliammai.co.in

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Valliammai Engineering Multicore Architecture Question

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Valliammai College Object Oriented Programming Question Bank

Unit I

Part A :
1.What is instruction level parallelism?
2. What are the advantages of loop unrolling?

3. What are the limitations of VLIW?
4. What is the use of branch-target buffer?
5. Distinguish between shared memory multiprocessor and message passing multiprocessor.
6. Differentiate multithreading computers from multiprocessor systems.
7. What is fine-grained multithreading and what is the advantage and disadvantages of fine- grained multithreading?
8.What is Amdhal’s law?
9.What is multi–core processor and what are the application areas of multi-core processors?
10. What is a Cell Processor?
11. State the principle of locality and its types.
12. What are the choices for encoding instruction set.
13. how the CPI is calculated?
14. What is loop unrolling?
15. Define multiprocessor cache coherence.
16. What are the approaches used for multithreading?
17. Which block should be replaced on a cache Miss?
18. How is cache performance improved?
19. What is hazard? State its types.
20. Mention the techniques available to measure the performance.

Part B :
1. Explain about trends in power with example.
2. Explain about classes of parallelism.
3. Explain instruction level parallelism and its exploitation
4. What are the Quantitative principle of computer design?
5. Explain different levels for parallel architectures
6. Explain Multithreading architectures
7. Explain about trends in power with example.
8. Explain about trends in technology with example.
9. Explain about trends in energy and cost with example.
10. Explain the limitations of single core architecture

Unit II

Part A :
1. What is a vector processor?
2. Define vector mask registers
3. How are the sparse matrices handled in vector architecture?
4. What is a stride?
5. What is a roofline model?
6. What are difference between banked and graphics memory
7. What are the primary components of VIMPS?
8. List the factors that depend on execution of vector operations
9. Define flexible chaining.
10. What is strip mining?
11. Why vector processor use memory banks?
12. Define CUDA thread and thread block
13. What is loop carry dependency?
14. Define fast double precision floating point arithmetic.
15. Differentiate vector and GPU architecture
16. What is gather/scatter in vector architecture?
17. Define the function of streaming SIMD Extension.
18. What is arithmetic intensity?
19. What are the special registers used in vector architecture?
20. What is the challenge of GPU programmer?

Part B :
1. Explain vector Architecture
2. Explain the vector execution time
3. Explain multimedia SIMD instruction set
4. Explain the graphics processing units
5. Explain the scheduling of threads in SIMD instructions
6. Explain Fermi GPU architecture
7. How to detect and enhance a loop level parallelism?
8. Explain GPU memory structures
9. Explain the GPU instruction Set architecture
10. Explain multimedia SIMD architecture

Unit III

Part A :
1. What is a thread? Explain thread level parallelism.
2. What are centralized shared memory architectures and symmetric shared memory multiprocessors?
3. What are distributed memory architectures?
4. What is a multicomputer?
5. What are message-passing multiprocessors?
6. What is RPC?
7. What are the advantages of different communication mechanisms?
8. What are the major advantages for message passing communication?
9. What is multiprocessor Cache Coherence?
10. What is cache coherence problem and when do you say a memory system is coherent? What are cache coherence protocols?
11. What is cache consistency?
12. What is write serialization?
13. What is snooping? What are the various snooping protocols?
14. What are write invalidate and write update protocols?
15. What are write through and write back caches?
16. What are ownership misses and coherence misses?
17. Compare true sharing and false sharing misses.
18. What are cold misses, coherence misses and conflict misses?
19. What is a working set effect?
20. Give a performance of snooping cache schemes.

Part B :
1. Explain in detail the symmetric shared memory architectures with reference to multiprocessor cache coherence problem.
2. Explain in detail the schemes available for enforcing coherence. Discuss its implementation techniques with suitable state diagrams.
3. With relevant graphs, discuss the performance of symmetric shared-memory multiprocessors for various workloads.
4. Explain in detail the distributed shared memory architecture highlighting the directory based cache coherence protocol. Substantiate your explanation with suitable examples and state diagrams.
5. Explain cache and memory states in multichip multicore processor
6. Explain in detail the memory consistency models.
7. Explain how thread level parallelism within a processor can be exploited? With suitable diagrams, explain simultaneous multithreading, its design challenges and potential performance enhancements.
8. Explain multiprocessor Cache Coherence?
9. Explain Multiprogramming and OS workload
10. Explainthe limitations in Symmetric shared memory multiprocessor and snooping protocols