College : Vardhaman College Of Engineering
Degree : B.Tech
Department : Computer Science & Engineering
Semester : IV
Subject : Computer Architecture & Organization
Document type : Question Paper
Website : vardhaman.org
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Vardhaman Computer Architecture Question Paper
VARDHAMAN COLLEGE OF ENGINEERING
Four Year B. Tech IV Semester Regular/Supplementary Examinations May – 2014
(Regulations : VCE-R11)
& Electrical and Electronics Engineering)
Date : 26
Time: 3 hours
Max Marks: 75
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
Related : Vardhaman College Of Engineering Metallurgy & Material Science B.Tech Question Paper : www.pdfquestion.in/6330.html
May – 2014
Unit – I
1. a) Convert the following pairs of decimal numbers to 5 bit, signed, 2’s complement, binary numbers and add them. State whether or not overflow occurs in each case.
i. -14 and 11
ii. -3 and -8
iii. -10 and -13 8M
b) What do you understand by stacks and subroutines? Explain in brief? 7M
2. a) By using the required parity generator/checker circuit, explain how parity checking can be used for the error detection. 7M
b) Convert the following binary number into decimal & octal number:
i. (00010.110)2
ii. (000.10110)2 8M
Unit – II :
3. a) Define addressing modes? Explain all the addressing modes with an example? 8M
b) With an example of each, explain memory reference instructions? 7M
4. a) With a neat block diagram, explain how the basic computer registers are connected to the common bus? 7M
b) With a neat diagram, explain the instruction pipeline processing in RISC architecture? 8M }}
Unit – III :
5. a) What is Micro programming? Give an example for Micro programming? 7M
b) Differentiate between hardwired & micro-programmed Computers? 8M
6. a) Perform the following:
i. (110.101) 2 = ( )10
ii. (1.10101)2 = ( )10
iii. (11010.1)2 = ( )10
iv. 110.10 x 10.1 7M
b) Perform the long hand binary division for the given binary number Divisor is 1111 and Dividend = 1100 8M
Unit – IV :
7. a) Draw the block diagram of a DMA controller and explain its functioning? 6M
b) Explain the organization of a 2M X 32 memory module using 512k X 8 static memory chips? 9M
8. a) Consider the page reference string 2 3 2 1 5 2 4 5 3 2 5 2. Find the number of page faults using the page replacement algorithms:
i. Optimal
ii. FIFO
iii. LRU
Assume that the number of frames available in the memory is 3. 10M
b) Consider the impact of the cache on overall performance of the computer. What is the average access time experienced by the processor with the hit rate and miss penalty?5M
Unit – V :
9. a) Describe the architecture of a shared memory multiprocessor? 7M
b) Draw and explain the 8×8 omega switch network? 8M
10. a) What do you mean by cache coherence? Mention the conditions under which cache coherence occurs. Explain, how cache coherence problem can be resolved by a snoopy cache controller? 7M
b) Define IPC? Mention the IPC methods. Explain any two methods in detail? 8M
December – 2013
B. Tech IV Semester Supplementary Examinations, :
(Regulations: VCE-R11
Computer Architecture And Organization :
(Common to Computer Science and Engineering, Information Technology, Electrical and Electronics Engineering & Electronics and Communication Engineering)
Date : 17 December, 2013
Time : 3 Hours
Max. Marks : 75
Answer ONE question from each Unit
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
Unit – I :
1.a) Draw the functional block diagram of a digital computer and explain functions of its various blocks. 7M
b) What do you understand by stacks & subroutines? Explain in brief. 8M
2. a) With a neat block diagram, explain the Basic Operational concept of a digital computer. 5M
b) What is register transfer language? Explain basic symbols used in register transfer. 10M
Unit – II :
3.a) For a RISC machine, the effective value of S is 1.25 and the average value of N is 200. If the clock rate is 500 MHz, calculate the total program execution time. 6M
b) What are the basic differences between a branch instruction, a call subroutine instruction and program interrupt? 9M
4. a) An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is 8M
i. Direct
ii. Immediate
iii. Relative
iv. Register indirect
v. Index with R1 as the index register
b) Convert the following numerical arithmetic expression into reverse Polish notation and show the stack operations for evaluating the numerical result (3+4)[10(2+6)+8]. 7M
Unit – III :
5. a) Draw a flowchart for adding or subtracting two floating –point binary numbers. 7M
b) Show the step-by-step multiplication process using Booth algorithm when the following binary numbers are multiplied (+15) x (-13). Assume 5-bit registers that hold signed numbers and draw the flowchart for the corresponding example. 8M
6. a) Define the following : 8M
i. Microoperation
ii. Microinstruction
iii. Microprogram
iv. Microcode
b) What is the difference between a microprocessor and a microprogram? Is it possible to design a microprocessor without a microprogram? Are all microprogrammed computers also microprocessors? 7M
Unit – IV :
7. a) What do you mean by Direct memory Access? Explain. Differentiate between Burst mode DMA and Cycle stealing DMA. 10M
b) With a diagram, explain the structure of a typical ROM cell.5M
8. a) Describe in words and by means of a block diagram how multiple matched words can be read out from an associative memory. 7M
b) A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words. 8M
i. How many bits are there in the tag, index, block and word fields of the address format?
ii. How many bits are there in each word of cache and how are they divided into functions? Include a valid bit.
iii. How many blocks can the cache accommodate?
Unit – 5 :
9.a) Describe the following terminology associated with multiprocessor: 8M
i. Mutual exclusion
ii. Critical section
iii. Hardware lock
iv. Semaphore
v. Test-and-set instruction
b) Construct a diagram for a 4X4 omega switching network. Show the switch setting required to connect input 3 to output 1. 7M
10. a)What is cache coherence, and why is it important in shared-memory multiprocessor system? How can the problem be resolved with a snoopy cache controller? 7M
b) Consider a bus topology in which two processors communicate through a buffer in shared memory. When one processor wishes to communicate with the other processor it puts the information in the memory buffer and sets a flag. Periodically, the other processor checks the flags to determine if it has information to receive. What can be done to ensure proper synchronization and to minimize the time between sending and receiving the information? 8M