Name of the College : Government Engineering College
Department : Computer Science Engineering
Subject Name : ELECTRICAL MACHINES-I
Year : May 2013
Degree : B.Tech
Sem : IV
Website : gecwyd.ac.in
Document Type : Model Question Paper
Download Model/Sample Question Paper : https://www.pdfquestion.in/uploads/pescemandya.org/4709-s4_eee_ns_may_2013.pdf
Electrical Machines-I :
lV Semester B,Tech. Degree (Reg./Sup.llmp. – lncluding Part Time) Examination, May 2013
(2007 Admn. Onwards)
Related : Government Engineering College Microprocessors & Microcontrollers B.Tech Question Paper : www.pdfquestion.in/4704.html
PT 2K6|2KG EE 405 : ELECTRICAL MACHINES – |
Time : 3 Hours
Max. Marks : 100
lnstruction : Answer all questions.
l. a) Define coil span, back pitch, front pitch and commutator pitch.
b) Explain the demagnetising effect of armature reaction.
c) A 4 pole d.c. generator has a lap-wound armature with 792 conductors. Find the speed at which it should run to generate 240V on no-load. Flux per pole is 0.012 wb.
d) What is meant by critical resistance ? How it is determined ?
e) What is back e.m.f. Discuss its significance.
f) Sketch the electrical and mechanical characteristics of d.c. series motor.
g) Derive the condition for maximum efficiency of a transformer.
h) Draw and explain the phasor diagram of a transformer supplying lagging power factor load. (8×5=40)
ll. a) Explain the advantages, disadvantages and applications of lap and wave windings.
b) A 4-pole generator has a wave wound armature withTZ?conductors, and it delivers 100 A on full load. lf the brush lead is 8″ find demagnetising and cross’magnetising ampere turns per pole.
c) Explain the commutation process in d.c. machine. Describe the various methods to improve commutation. 15
lll. a) Draw and explain the powerflow diagram of a d.c. generator. 5
b) Explain the conditions for building up of voltage in d.c. shunt generator. 4
c) Sketch and explain the internal and externalcharacteristics of d.c. shunt generator 6
OR
d) Derive the e.m.f. equation of a d.c. generator. 5
e) Two shunt generators with no load voltage 125 are running in parallel. The external characteristics are linear. The rating of the generators are 25 kW, 1 19 V and 200 kW 1 16 V. Find bus bar voltage when the load is 3500 A (total).
How the load is divided between them ? 10
lV. a) Derive the torque equation of a d.c. motor.
b) Explain the operation and design of three point starter.
OR
c) Explain retardation test.
d) The no load test on 44.76kW,220 V-dc shunt motor gave the following result
ln put current = 13.25 A, Field current = 2.55 A, Armature resistahce = 0.032, brush drop = 2 V. Estimate full load efficiency.
V. a) Drawthe circuit diagrams and explain the procedure forconducting O.C. and S.C. tests on single phase transformed. Also explain the determination of equivalent circuit parameters from the test results.
OR
A230140 V, 3 KVA transformer gave the following results :
O.C. Test : 40 V, 2 A,100 W
S.C. Test : 15 V, 13 A, 120 W
Determine the regulation and efficiency a F.L. 0.8 pf lagging. Write a note on switching transients.
Examination, November 2014 :
Electronic Circuits And Systems :
Time : 3 Hours
Max. Marks : 100
Part-A :
Answer aII questions.
1. a) Explain how diode acts as a switch.
b) For an input of 10 V (P-P) J draw and explain a negative clam per clamped at-2 volts.
c) Explain the working of a CMOS Nand gate.
d) Write a short note on ECL.
e) What is a sample and hold circuit? Explain.
f) Explain about the different types of RAM.
g) What is trle ideal bandwidth required for wide band FM transmission? Explain.
h) What is noise figure? Explain its importance. (8)(5=40)
PART-B :
2. a) i) With neat diagram and necessary waveform explain the working of an a stable multi vibrator using transistors. 9 ii) Explain the working of transistor as a switch. 6 OR
b) Draw and explain the working of a Miller and Bootstrap sweep generators. Also write the difference. 15
3. a) i) Compare and contrast between different types of integration. 10
ii) What is the difference between positive logic and negative logic level? Explain. 5
OR
b) What is the need of interfacing in logic circuits? Also explain with diagram how interfacing is done between CMOS logic and TTL logic. 15