Name of the Institute : Babu Banarasi Das National Institute of Technology & Management
Degree : BCA
Department : Computer Applications
Subject Code/Name : (BCA-T113) Digital Electronics
Year : 1st
Semester : 1st
Document Type : Question Bank
Website : bbdnitm.ac.in
Download Model/Sample Question Paper :https://www.pdfquestion.in/uploads/bbdnitm.ac.in/3164-BCA-T-113-Digital-Electronics-Question-Bank.pdf
BBDNITM Digital Electronics Question Paper
1. Complement of a variable is always its .
2. Determine the logic gate to implement the following terms–ABC, A+B+C?
3. What is parity generation ?
Related : BBDNITM BCA304 System Analysis & Design BCA Question Bank : www.pdfquestion.in/3167.html
4. Add the following BCD numbers— 1001 and 0100?
5. Equivalent Gray code representation of AC2H.?
6. A NAND gate becomes gate when used with negative logic ?
7. Implement the logic equation Y = _ C’ B A’ + C’ B A + CBA with a multiplexer.
8. Distributive law states that .
9. Represent standard SOP & POS form?
10. OR operation can be produced by gates.
11. is known as a universal gate as can be used to implement all Boolean expressions.
12. Simplify the expression AB + A( B + C ) + B ( B + C )?
13. a 3 variable karnaugh map has cells.(eight cells)
14. On karnaugh map grouping of 0’s produces (POS expression).
15. State distributive law?
16. State De Morgans theorem?
17. Give an example of SOP form?
18. According to assosiative law .[A(BC)=AB(C)]
19. A logic circuit with an output X=AB’C+AC’ consist of gates, gates and inverters.(two,one,two)
20. The OR operations can be produced with two gates or three gates.(NOR,NAND)
21. The AND operation can be produced with two gates.(NAND)
22. What is a decoder?(a digital circuit that converts coded informationinto a familiar or noncoded form)
23. Define demultiplexer?(a circuit that switches digital data from one input line to several output lines in a specified time sequence )
24. Difference between half adder and full adder?
25. A half adder is characterized by inputs and_ outputs.(two,two)
26. A full adder is characterized by inputs and outputs.(three,two)
27. A 4 bit parallel adder can add 4 bit binary numbers.(two)
28. Data selectors are basically same as .(multiplexers)
29. A multiplexer has data inputs, data outputs and selection inputs.(several,one)
30. What is 1’s complement.
31. What is 2’s complement.
32. Define Gray code with example.
33. What Karnaugh Map.How it represent.
34. Obtain the following operations using NAND gates.
a) NOT b) AND c) OR
35. Obtain the following operations using NOR gates.
a) NOT b) AND c) OR
36. For the logic expression Y = A B + A B. Obtain the truth table and Name the operation performed.
37. Prove using De Morgan’s theorems. AB + CD = AB. CD
38. Prove using De Morgan’s theorems. (A+B) + (C+D)
39. Define De Morgan’s theorems.
40. Verify the following gate with Truth Table.
** OR,
** AND
** NOT
** NAND
** NOR
** XOR
** XNOR
41. What is a digital signal.
42. Differentiate between analog & digital signals.
43. Convert the binary number into octal number 11011100.101010
44. Add the binary numbers 1011 + 1101 , 1010.1101 + 101.01
45. Subtraction the binary numbers 1011 – 0110 , 1110 – 1001
46. Find 1’s complement of the numbers. a) 10100111 b) 01111 47. Find the 2’s complement of the number 01100100
48. Represent the following decimal numbers in the signed binary number system. +29 & -29
49. Perform the subtraction using 2’s complementary arithmetic 11011 – 11001
50. Convert the BCD number to their decimal equivalent. 0100 0011 1001
51. What is Excess-3 Code. and perform Excess –3 code of 14.
52. Convert the binary number into Gray code. 110100
53. Convert the Gray code into binary number 101110
54. Define ASCII Code.
55. Define EBCDIC Code.
56. What is a min term & max term.
57. What is the parity of the binary number 100110011.
58. Implement the Boolean expressions using minimum number of gates. Y = ABC + ABC
59. Draw & explain :
** binary half adder.
** binary full adder.
** binary half subtractor.
** binary full subtractor
60. How can full adder be realized using two half adders
61. Show how to connect NAND gate to get an AND gate.
62. Perform 9’s complement of 234.
63. Perform 10’s complement of 567.
64. Explain tri-state logic.
65. Explain SOP form and POS form of logic expression.
66. What is a Karnaugh –map and what for it is used.
67. Convert (1001110)2 to its octal equivalent.
68. Convert (247.36)8 to equivalent hex number.
69. What is meant by parity of a digital word.
70. What is AND-OR realization.