Name of the College : Kings College Of Engineering
Department : Electronics & Communication Engineering
Subject : VLSI Design
Website : kings.ac.in
Document Type : Question Bank
Download Model/Sample Question Paper : https://www.pdfquestion.in/uploads/ki…I%20DESIGN.pdf
Kings VLSI Design Question Paper
Unit – I
MOS Transistor Theory And Process Technology :
Part A :(2 Marks)
1. What is meant by “Epitaxy”?
2. What is isolation?
3. What is the special feature of Twin-Tub process?
Related : Kings College of Engineering EC1011 OPTO Electronic Devices Question Bank : www.pdfquestion.in/1309.html
4. What are the various processes used in SOI?
5. What is siliside?
6. What is LDD?
7. What is LOCOS?
8. Give the advantages of IC
9. What is Depletion mode Device?
10. Name the four generations of Integration Circuits?
11. Name the types of Integrated Circuits
12. Give the basic process for IC fabrication.
13. What are the various steps in Silicon wafer preparation?
14. What are the advantages of Silicon-on-Insulator process?
15. What are the advantages of CMOS process?
16. What are the different MOS layers?
17. Why NMOS technology is preferred more than PMOS technology?
18. What are the different operating regions an MOS transistor?
Part-B : (16 Marks)
1.a) Explain the operation of NMOS Enhancement transistor (8)
b) Derive the Threshold voltage for NMOS Enhancement transistor (8)
2. a) Explain about the body effect of MOS transistors. (6)
b) Derive the design equations for MOS devices (4)
c) What do you mean by channel length modulation? Explain. (6)
3. a) Explain the second order effects with their equations. (10)
b) Explain small signal AC characteristics with its design equations. (6)
4. Explain the fabrication of PMOS transistor and its substrate fabrication
Process. (16)
5. Explain different fabrication process of CMOS transistor (16)
Unit – II
Part- A :(2 Marks)
1. Define noise margin.
2. Define Rise Time.
3. What is body effect?
4. What is low noise margin?
5. What is stick diagram?
6. What are Lambda (O) – based design rules?
7. Define a super buffer.
8. Give the CMOS inverter DC transfer characteristics and operating regions
9. Give the various color coding used in stick diagram?
10. Define Delay time
11. Give the different symbols for transmission gate.
12. Compare between CMOS and bipolar technologies.
13. What are the static properties of complementary CMOS Gates
14. Draw the circuit of a nMOS inverter
15. Draw the circuit of a CMOS inverter
Part-B : (16 Marks)
1. List out the layout design rule. Draw the physical layout for one basic gate and two universal gates. (16)
2. Explain the complimentary CMOS inverter DC characteristics. (16)
3. Write short notes on :
(a) Noise Margin (10)
(b) Rise Time (3)
(c) Fall Time (3)
4. Briefly discuss about the following :
a) Pseudo-NMOS inverter (8)
b) Saturated Load inverters (4)
c) Cascade inverter (4)
5. a. Explain the concept of static and dynamic CMOS design (8)
b. Explain the construction and operation of transmission gates (8)
Unit – III
Part-A :(2 Marks)
1. What are the issues to be considered for circuit characterization and performance estimation?
2. Give the formula for resistance of a uniform slab of conducting material.
3. What are the factors to be considered for calculating total load capacitance on the output of a CMOS gate?
4. What are the components of Power dissipation?
5. What is meant by path electrical effort?
6. Define crosstalk.
7. Define scaling. What are the factors to be considered for transistor scaling?
8. Define constant voltage scaling.
9. What are the sources to be considered for design margin?
Part-B : (16 Marks)
1. Explain in detail about the following :
a) Resistance estimation (8)
b) Inductance estimation (8)
2. Explain about routing capacitance with neat diagram. (16)
3. With neat diagram explain about power dissipation. (16)
4. Briefly explain about the following :
a) CMOS transistor sizing (8)
b) Design margining (8)
5. Explain about scaling of MOS transistor dimensions and charge sharing. (16)